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lead (pb) free product - rohs compliant red pdsp2110 yellow pdsp2111 super-red PDSP2112 green pdsp2113 high efficiency green pdsp2114 5.10 mm (0.200") 8-character 5x7 dot matrix parallel input alphanumeric intelligent display? devices 2006-01-23 1 description the pdsp2110 (red), pdsp2111 (yellow), PDSP2112 (super-red), pdsp2113 (green), and pdsp2114 (high efficiency green) are eight digit, 5 x 7 dot matrix, parallel input, alphanumeric intelligent display devices. the 5.10 mm (0.200??) high digits are packaged in a rugged, high quality, optically transparent, 15.24 mm (0.6??) lead spacing, 28 pin plastic dip. the on-board cmos has a built-in 256 character rom. both pages are mask programmable for 256 custom characters.the first page of rom of a standard product contains 128 characters including ascii, selected euro - pean and scientific symbols. the second page contains katakana japanese characters, more european charac - ters, avionics, and other graphic symbols. the pdsp211x is designed for standard microprocessor interface techniques, and is fully ttl compatible. the clock i/o and clock select pins allow the user to cas - cade multiple display modules. features eight 5.10 mm (0.200??) dot matrix characters in red, yellow, super-red, green, high efficiency green built-in 2 page, 256 character rom, both pages are mask programmable for custom fonts readable from 2.5 meters (8 feet) built-in decoders, multiplexers and drivers wide viewing angle, x axis 55 , y axis 65 programmable features: ? individual flashing character ? full display blinking ? multi-level dimming and blanking ? clear function ? lamp test internal or external clock end stackable dual-in-line plastic package
2006-01-23 2 pdsp2110, pdsp2111, pdsp2 112, pdsp2113, pdsp2114 package outlines dimensions in mm (inch) ordering information type color of emission character height mm (inch) ordering code pdsp2110 red 5.10 (0.200) q68000a8474 pdsp2111 yellow q68000a8503 PDSP2112 super-red q68000a8504 pdsp2113 green q68000a8505 pdsp2114 high efficiency green q68000a8533 idod5020 19.58 (0.771) 5.34 (0.210) 42.67 (1.680) max. 2.67 (0.105) 4.81 (0.189) 9.8 (0.386) pin 1 indicator 5.31 (0.209) 15.24 (0.600) 0.3 (0.012) typ. 2.19 (0.086) 4.79 (0.189) 2.54 (0.100) typ. 0.46 (0.018) typ. 4.06 (0.160) 0.5 (0.020) pdsp211x z osram yyww v y part number code eia date intensity code color bin
pdsp2110, pdsp2111, pdsp2 112, pdsp2113, pdsp2114 2006-01-23 3 maximum ratings ( t a =25 c) parameter symbol value unit operating temperature range t op ? 40 ? + 85 c storage temperature range t stg ? 40 ? + 100 c dc supply voltage, v cc to gnd (max. voltage with no leds on) v cc -0.5 to + 7.0 v input voltage levels relative to gnd -0.5 to v cc + 0.5 v solder temperature 1.59 mm (0.063?) below seating plane, t < 5.0 s t s 260 c relative humidity (non-condensing) 85 % optical characteristics at 25 c ( v cc =5.0 v at 100% brightness level) description symbol values unit red pdsp2110 yellow pdsp2111 super-red PDSP2112 green pdsp2113 high efficiency green pdsp2114 peak luminous intensity 1) (min.) (typ.) i vpeak 70 90 130 210 150 330 150 260 200 510 cd/dot cd/dot peak wavelength (typ.) peak 660 583 630 565 568 nm dominant wavelength (typ.) dom 639 585 626 570 574 nm note: 1) peak luminous intensity is measured at t a = t j =25 c. no time is allowed for the device to warm up prior to measurement.
pdsp2110, pdsp2111, pdsp2 112, pdsp2113, pdsp2114 2006-01-23 4 enlarged character font dimensions in inch (mm) write cycle timing diagram notes: 1. all input voltages are v il =0.8 v, v ih =2.0 v. 2. these wave forms are not edge triggered. 3. t bw = t as + t ah idod5202 c1 c2 c3 c4 c5 r1 r2 r3 r4 r5 r6 r7 2.85 (0.112) 0.76 (0.030) typ. 0.65 (0.026) typ. 4.81 (0.189) 0.254 (0.010) idtc5054 data wait data write control word - clear bit enabled wait 130 ns clear bit enabled write control word - switching specifications (over operating temperature range and v cc =4.5 v) symbol description min. units t bw time between writes 30 ns t acc (2) display access time 130 ns t as address setup time 10 ns t ces chip enable setup time 0 ns t ah address hold time 20 ns t ceh chip enable hold time 0 ns t w write active time 100 ns t ds data valid prior to rising edge of write 50 ns t dh data hold time 20 ns t rc (1) reset active time 300 ns t clr (3 ) clear cycle time 3.0 s notes: 1) wait 300 ns min. after the reset function is turned off. 2) t acc = t as + t w + t ah 3) the clear cycle time may be shortened by writing a second control word with the clear bit disabled, 160 ns after the first control word that enabled the clear bit. the flash ram and character ram may not be accessed until the clear cycle is complete. tas tah tceh tces tw tdh tds tbw ce d7-d0 wr fl, a3-a0 see notes tacc see notes see notes see notes
pdsp2110, pdsp2111, pdsp2 112, pdsp2113, pdsp2114 2006-01-23 5 electrical characteristics at 25 c parameters limits conditions min. typ. max. units v cc 4.5 5.0 5.5 v ? i cc blank ? 0.5 1.0 ma v cc =5.0 v, v in =5.0 v i cc 8 digits 1) 12 dots/character ? 200 255 ma v cc =5.0 v, ?v? displayed in all eight digits i cc 8 digits 1) 20 dots/character ? 300 370 ma v cc =5.0 v, ?#? displayed in all eight digits i ip current (with pull-up) ? 11 18 a v cc =5.0 v, v in =0 v to v cc ( wr , ce , fl , rst , clksel ) i, input leakage current (no pull-up) ? ? 1.0 a v cc =5.0 v, v in =0 v to v cc (clk i/o, a0?a3, d0?d7) v ih input voltage high 2.0 ? v cc +0.3 v v cc =4.5 v to 5.5 v v il input voltage low gnd ?0.3 ? 0.8 v v cc =4.5 v to 5.5 v v ol output voltage low (clock pin) ? ? 0.4 v v cc =4.5 v to 5.5 v i ol =1.6 ma v oh output voltage high (clock pin) 2.4 ? ? v v cc =4.5 v to 5.5 v i oh =40 ma i oh output current high (clock i/o) ?0.9 ? ? ma v cc =4.5 v, v oh =?2.4 v i ol output current low (clock i/o) 1.6 2.0 ? ma v cc =4.5 v, v ol =?0.4 v jc thermal resistance junction to case ? 25 ? c/w ? f ext external clock input frequency 2) 28 ? 81.14 khz v cc =5.0 v, clksel =0 f osc internal clock output frequency 2) 28 ? 81.14 khz v cc =5.0 v, clksel =1 clock i/ o buss loading ? ? 240 pf ? clock out rise time ? ? 500 ns v cc =4.5 v, v oh =2.4 v clock out fall time ? ? 500 ns v cc =4.5 v, v ol =0.4 v fm, digit multiplex frequency 125 256 362.5 hz ? blinking rate 0.98 2.0 2.83 hz ? notes: 1) average i cc measured at full brightness. peak i cc =2 x i avg i cc (# displayed). 2) internal/external frequency duty factor is 50%.
pdsp2110, pdsp2111, pdsp2 112, pdsp2113, pdsp2114 2006-01-23 6 top view pin assignments pin function pin function 1 rst 28 d7 2 fl 27 d6 3 a0 26 d5 4 a1 25 d4 5 a2 24 d3 6 a3 23 d2 7 substr. bias 22 no pin 8 21 9 20 d1 10 no connect 19 d0 11 clksel 18 no connect 12 clk i/o 17 ce 13 wr 16 gnd (logic) 14 v cc 15 gnd (supply) idpa5116 01234567 digit pins 1 28 pins 15 14 pin definitions pin function definition 1 rst used for initialization of a display and sychronization of blinking for multiple displays 2 fl low input accesses the flash ram 3 a0 address input lsb 4 a1 address input 5 a2 address input msb 6 a3 mode selector 7-9 substr. bias used to bias ic substrate, must be connected to v cc . can't be used to supply power to display. 10 no connect ? 11 clksel selects internal/external clock source 12 clk i/o outputs master clock or inputs external clock 13 wr a low will write data into the display if ce is low 14 v cc positive power supply input 15 gnd analog ground for led drivers 16 gnd digital ground for internal logic 17 ce enables access to the display 18 no connect ? 19 d0 data input lsb 20 d1 data input 21 no pin ? 22 23 d2 data input 24 d3 25 d4 26 d5 27 d6 28 d7 data input msb, selects rom, page 1 or 2
pdsp2110, pdsp2111, pdsp2 112, pdsp2113, pdsp2114 2006-01-23 7 cascading the pdsp211x displays idcd5031 rd wr fl clk clk display cc v d0-d7 a0-a4 ce up to 14 more displays in between i/o sel ce display d0-d7 a0-a4 data i/o address decoder address address decode chip 1 to 14 a6 a7 a9 wr fl rst rst 0 15 rd rst rd wr fl clk sel clk i/o a8
2006-01-23 8 pdsp2110, pdsp2111, pdsp2 112, pdsp2113, pdsp2114 character set rom page 1 (d7= 0) rom page 2 (d7=1) idcs5093 ascii code d0 d1 d2 d3 hex d4 d5 d6 000 0 1 1 0 0 2 010 3 011 4 100 5 101 6 110 7 111 0 0 0 0 0 1 0 0 1 0 2 0 0 0 1 3 0 0 1 1 4 0 1 0 0 5 0 1 1 0 6 0 1 0 1 7 0 1 1 1 8 1 0 0 0 9 1 0 1 0 a 1 0 0 1 b 1 0 1 1 c 1 1 0 0 d 1 1 1 0 e 1 1 0 1 f 1 1 1 1 idcs5094 asc|| code d0 d1 d2 d3 hex d4 d5 d6 000 0 1 1 0 0 2 010 3 011 4 100 5 101 6 110 7 111 0 0 0 0 0 1 0 0 1 0 2 0 0 0 1 3 0 0 1 1 4 0 1 0 0 5 0 1 1 0 6 0 1 0 1 7 0 1 1 1 8 1 0 0 0 9 1 0 1 0 a 1 0 0 1 b 1 0 1 1 c 1 1 0 0 d 1 1 1 0 e 1 1 0 1 f 1 1 1 1
pdsp2110, pdsp2111, pdsp2 112, pdsp2113, pdsp2114 2006-01-23 9 block diagram functional description the pdsp211x block diagram is comprised of the following major blocks and registers. display memory consists of a 8 x 8 bit ram block. each of the eight 8-bit words holds the 7-bit ascii data (bit d0-d6). the 8th bit, d7 selects 1 of the 2 pages of character rom. d7=0 selects page 1 of the rom and d7=1 selects page 2 of the rom. a3=1. rst can be used to initialize display operation upon power up or during normal operation. when activated, rst will clear the flash ram and control word register (00h) and reset the internal counter. all eight display memory locations will be set to 20h to show blanks in all digits. fl pin enables access to the flash ram . the flash ram will set (d0=0) or reset (d0=0) flashing of the character addressed by a0-a2. the 1 x 8 bit control word ram is loaded with attribute data if a3=0. the control word logic decodes attribute data for proper imple - mentation. character rom is designed for two pages of 128 characters each. both pages of the rom are mask programmable for custom fonts. on the standard product page one contains standard ascii, selected european characters and some scientific symbols. page two contains katakana characters, more european characters, avi - onics, and other graphic symbols. the clock source could either be the internal oscillator ( clksel =1) of the device or an external clock ( clksel =0) could be an input from another pdsp211x display for the synchroniza - tion of blinking for multiple displays. the display multiplexer controls the row drivers so no additional logic is required for a display system. the display has eight digits. each digit has 35 leds clustered into a 5 x 7 dot matrix. theory of operation the pdsp211x programmable display is designed to work with all major microprocessors. data entry is via an eight bit parallel bus. three bits of address route the data to the proper digit location in the ram. standard control signals like wr and ce allow the data to be written into the display. d0- d7 data bits are used for both ascii and control word data input. a3 acts as the mode selector. if a3=0, d0-d7 load the ram with control word data. if a3=1, d0-d7 will load the ram with ascii and page select data. in the later mode, d7=0 selects page 1 of character rom and d7=1 selects page 2 of character rom. for normal operation fl pin should be held high. when fl is held low, flash ram is accessed to set character blinking. the seven bit ascii code is decoded by the character rom to generate column data. twenty columns worth of data is sent out each display cycle and it takes fourteen display cycles to write into eight digits. the rows are being multiplexed in two sets of seven rows each. the internal timing and control logic synchronizes the turning on of rows and presentation of column data to assure proper display operation. idbd5068 display memory 8 x 8 bits d0 d4 d2 d1 d3 d6 d5 d7 control word decode logic latches 7-bit code flash ram 8 x 1 bit address address decoder a0 a1 a2 a3 wr ce fl column decoder character decode (4.48 kbits) rom 1 ascii 128 x 7 bit ascii character (4.48 kbits) decode 128 x 7 bit rom 2 row decoder data master slave latches digit 0 to 8 column drivers 0 to 8 for digit column lines control word ascii osc counter 32 counter 7 counter 128 clk i/o clksel rst mux rate rate blink row control logic & row drivers control timing & logic rows 0 display 3 12 0 to 13 6 5 4 7 columns 0 to 19
pdsp2110, pdsp2111, pdsp2 112, pdsp2113, pdsp2114 2006-01-23 10 power up sequence upon power up display will come on at random. thus the display should be reset on power-up. the reset will clear the flash ram, control word register and reset the internal counter. all the dig - its will show blanks and display brightness level will be 100%. microprocessor interface the interface to a microprocessor is through the 8-bit data bus (d0-d7), the 4-bit address bus (a0-a3) and control lines fl , ce and wr . to write data (ascii/ control word) into the display ce should be held low, address and data signals stable and wr should be brought low. the control word is decoded by the control word decode logic. each code has a different function. the code for display brightness changes the duty cycle for the column drivers. the peak led cur - rent stays the same but the average led current diminishes depending on the intensity level. the character flash enable causes 2.0 hz coming out of the counter to be anded with column drive signal and makes the col - umn driver to cycle at 2.0 hz. thus the character flashes at 2.0 hz. the display blink works the same way as the flash enable but causes all twenty column drivers to cycle at 2.0 hz thereby making all eight digits to blink at 2.0 hz. the lamp test causes the column drivers to run at 1/2 duty cycle thus all the leds in all eight digits turn on at 50% intensity. clear bit clears the character ram and writes a blank into the dis - play memory. it however does not clear the control word. ascii data or control word data ca n be written into the display at this point. for multiple display operation, clk i/o must be properly selected. clk i/o will output the internal clock if clksel =1, or will allow input from an external clock if clksel =0. data input commands signals ce wr fl a3 a2 a1 a0 operation 1 xxxxxx x 1 xxxxx no operation no operation 0 0 10000 write control register 0 01100 0 0 01100 1 0 01101 0 0 01101 1 0 01110 0 0 01110 1 0 11110 0 0 01111 1 digit 0 (left) digit 1 digit 2 digit 3 digit 4 digit 5 digit 6 digit 7 (right) write display data to user ram and page select register d0?d6=ascii data d7=0 select rom 1 d7=1 select rom 2 0 00x000 0 00x001 0 00x010 0 00x111 0 00x100 0 00x101 0 00x110 0 00x111 digit 0 (left) digit 1 digit 2 digit 3 digit 4 digit 5 digit 6 digit 7 (right) write flash ram register d0=0 flashing charac. off d0=1 flashing charac. on d1?d7=x x=don?t care
pdsp2110, pdsp2111, pdsp2 112, pdsp2113, pdsp2114 2006-01-23 11 control word format flash ram function character flash is controlled by fl pin, bit d0 and control word bit d3. combination of fl being low, proper digit address and d0 being high will write a flash bit into the flash ram register. in the control word mode when d3 is brought high, the above mentioned character will flash. display brightness the display can be programmed to vary between blank, 13%, 20%, 27%, 40%, 53%, 80% and full brightness. bits d0, d1 and d2 control the display brightness. ce wr fl a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 display brightness 001 001 001 001 001 001 001 001 0x x x 0x x x 0x x x 0x x x 0x x x 0x x x 0x x x 0x x x 0 0xxx0 00 0 0xxx0 01 0 0xxx0 10 0 0xxx0 11 0 0xxx1 00 0 0xxx1 01 0 0xxx1 10 0 0xxx1 11 100% brightness 80% brightness 53% brightness 40% brightness 27% brightness 20% brightness 13% brightness blank display x=don?t care setting the flash bit ce wr fl a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 operation 000 000 xa a a xa a a x xxxxxx0 x xxxxxx1 flash ram disabled flash ram enabled x=don?t care a=selected address character flash control word ce wr fl a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 operation 001 001 0x x x 0x x x 0 0x00bbb 0 0x01bbb disable flashing character enable flashing character x=don?t care b=selected brightness display blinking blinking function is independent of flash function. when d4 is held high, entire display blinks at 2.0 hz. ce wr fl a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 operation 001 001 0x x x 0x x x 0 0x00bbb 0 0x10bbb display blinking disabled display blinking enabled x=don?t care b=selected brightness lamp test bit d6 when brought high will cause all the leds in all eight digits to light up at 53% brightness. selecting or de-selecting lamp test bit has no effect on the display memory. ce wr fl a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 operation 001 001 0x x x 0x x x 0 0x0 xxxx 0 1x00xxx lamp test disabled lamp test enabled x=don?t care
2006-01-23 12 pdsp2110, pdsp2111, pdsp2 112, pdsp2113, pdsp2114 control word format clear function clear function will clear the display. the flash ram will be set to all zeros. an ascii blank co de (20h) will be written into t he display memory. the user must wait 3.0 ms or write a new control word to the display with control word bit d7 = 0 to disable clear before writing any data to the display memory, otherwise all new data to the display memory will remain cleared . see switching specifications for clear function timing. ce wr fl a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 operation 001 001 0x x x 0x x x 0 xxxxxxx 1 xxxxxxx clear disabled clear user ram, page ram, flash ram and display x=don?t care idcw5164 enable blink lamp enable brightness control d7 d6 d5 d4 d3 d2 d1 d0 d1 d0 brightness 100% 00 80% 01 1 53% 0 1 40% 1 disable flashing character flash enable d3 0 enable flashing character 1 enable blinking display disable blinking display blinking display d4 1 0 disable lamp test enable lamp test (all dots on at 53% brightness) lamp test enable clear (clear data ram, page ram, flash ram) disable clear 0 1 clear enable d7 clear flash enable d2 0 0 0 0 27% 0% blank 11 1 1 1 0 10 1 0 1 20% 13% 0 0 1 d6 test not used
pdsp2110, pdsp2111, pdsp2 112, pdsp2113, pdsp2114 2006-01-23 13 electrical and mechanical considerations voltage transient suppression for best results power the display and the components that inter - face with the display to avoid logic inputs higher than v cc . addi - tionally, the leds may cause transients in the power supply line while they change display states. the common practice is to place a parallel combination of a 0.01 f and a 22 f capacitor between v cc and gnd for all display packages. esd protection the input protection structure of the pdsp2110/1/2/3/4 provides significant protection against esd damage. it is capable of with - standing discharges greater than 2.0 kv. take all the standard pre - cautions, normal for cmos components. these include properly grounding personnel, tools, tables, and transport carriers that come in contact with unshielded parts. if these conditions are not, or can - not be met, keep the leads of the device shorted together or the parts in anti-static packaging. soldering considerations the pdsp2110/1/2/3/4 can be hand soldered with sn63 solder using a grounded iron set to 260 c. wave soldering is also possible following these conditions: pre - heat that does not exceed 93 c on the solder side of the pc board or a package surface temperature of 85 c. water soluble organic acid flux (except carboxylic acid) or rosin-based rma flux without alcohol can be used. wave temperature of 245 c 5 c with a dwell between 1.5 sec. to 3.0 sec. exposure to the wave should not exceed temperatures above 260c for five seconds at 1.59 mm (0.063") below the seating plane. the packages should not be immersed in the wave. post solder cleaning procedures the least offensive cleaning solution is hot d.i. water (60 c) for less than 15 minutes. addition of mild saponifiers is acceptable. do not use commercial dishwasher detergents. for faster cleaning, solvents may be used. exercise care in choos - ing solvents as some may chemically attack the nylon package. maximum exposure should not exceed two minutes at elevated temperatures. acceptable solvents are tf (trichorotrifluorethane), ta, 111 trichloroethane, and unheated acetone. (1) note: 1) acceptable commercial solvents are: basic tf, arklone, p. genesolv, d. genesolv da, blaco-tron tf and blaco-tron ta. unacceptable solvents contain alcohol, methanol, methylene chloride, ethanol, tp35, tcm, tmc, tms+, te, or tes. since many commercial mixtures exist, contact a solvent vendor for chemical composition information. some major solvent manufac - turers are: allied chemical corporation, specialty chemical divi - sion, morristown, nj; baron-blakeslee, chicago, il; dow chemical, midland, mi; e.i. dupont de nemours & co., wilming - ton, de. for further information refer to appnotes 18 and 19 at www.osram-os.com an alternative to soldering and cleaning the display modules is to use sockets. naturally, 28 pin dip sockets 15.24 mm (0.600") wide with 2.54 mm (0.100") centers work well for single displays. multiple display assemblies are best handled by longer sip sock - ets or dip sockets when available for uniform package alignment. socket manufacturers are aries electronics, inc., frenchtown, nj; garry manufacturing, new brunswick, nj; robinson-nugent, new albany, in; and samtec electronic hardward, new albany, in. for further information refer to appnote 22 at www.osram-os.com optical considerations the 5.10 mm (0.200") high character of the pdsp211x gives read - ability up to eight feet. proper filt er selection enhances readability over this distance. using filters emphasizes the contrast ratio between a lit led and the character background. this will increase the discrimination of different characters. the only limit ation is cost. take into consider - ation the ambient lighting environment for the best cost/benefit ratio for filters. incandescent (with almost no green) or fluorescent (with almost no red) lights do not have the flat spectral response of sunlight. plas - tic band-pass filters are an inexpensive and effective way to strengthen contrast ratios. the pdsp2110/2112 are red/super-red displays and should be matched with long wavelength pass filter in the 570 nm to 590 nm range. the pdsp2111/2113/2114 should be matched with a yellow-green band-pass filter that peaks at 565 nm. for displays of multiple colors, neutral density grey filters offer the best compromise. additional contrast enhancement is gained by shading the dis - plays. plastic band-pass filters with built-in louvers offer the next step up in contrast improvement. plastic filters can be improved further with anti-reflective coatings to reduce glare. the trade-off is fuzzy characters. mounting the filters close to the display reduces this effect. take care not to overheat the plastic filter by allowing for proper air flow. optimal filter enhancements are gained by using circular polar - ized, anti-reflective, band-pass filters. the circular polarizing fur - ther enhances contrast by reducing the light that travels through the filter and reflects back off the display to less than 1%. several filter manufacturers supply quality filter materials. some of them are: panelgraphic corporation, w. caldwell, nj; sgl homa - lite, wilmington, de; 3m company, visual products division, st. paul, mn; polaroid corporation, polarizer division, cambridge, ma; marks polarized corporation, deer park, ny, hoya optics, inc., fremont, ca. one last note on mounting filters: recessing displays and bezel assemblies is an inexpensive way to provide a shading effect in overhead lighting situations. several bezel manufacturers are: r.m.f. products, batavia, il; no bex components, griffith plastic corp., burlingame, ca; photo chemical products of california, santa monica, ca; i.e.e.?atlas, van nuys, ca.
2006-01-23 14 pdsp2110, pdsp2111, pdsp2 112, pdsp2113, pdsp2114 p ublished by osram opto semiconductors gmbh wernerwerkstrasse 2, d-93049 regensburg www.osram-os.com ? all rights reserved. attention please! the information describes the type of component and shall not be considered as assured characteristics. terms of delivery and rights to change design reserved. due to technical requirements components may contain dangerous substances. for informati on on the types in question please contact our sales organization. if printed or downloaded, please find the latest version in the internet. packing please use the recycling operators known to you. we can also help you ? get in touch with your nearest sales office. by agreement we will take packing material back, if it is sorted. you must bear the costs of transport. for packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. components used in life-support devices or systems must be expressly authorized for such purpose! critical components 1) may only be used in life-support devices or systems 2) with the express written approval of osram os. 1) a critical component is a component used in a life-support devi ce or system whose failure can reasonably be expected to cause t he failure of that life-support device or system, or to affect its safety or the effectiveness of that device or system. 2) life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and susta in human life. if they fail, it is reasonable to assume that the health and the life of the user may be endangered. revision history: 2006-01-23 previous version: 2005-01-10 page subjects (major changes since last revision) date of change all lead free device 2006-01-23

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